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features ? serial peripheral interface (spi) compatible ? supports spi modes 0 (0,0) and 3 (1,1) ? data sheet describes mode 0 operation ? low-voltage and standard-voltage operation ?v cc = 1.8v to 5.5v ? 20 mhz clock rate (5v) ? 8-byte page mode ? block write protection ? protect 1/4, 1/2, or entire array ? write protect ( wp) pin and write disable instructions for both hardware and software data protection ? self-timed write cycle (5 ms max) ? high reliability ? endurance: one million write cycles ? data retention: 100 years ? green (pb/halogen-free/rohs compliant) packaging options ? die sales: wafer form, waffle pack, bumped wafers description the at25010b/020b/040b provides 1024/2048/4096 bits of serial electrically eras- able programmable read-only memory (eeprom) organized as 128/256/512 words of 8 bits each. the device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. the at25010b/020b/040b is available in space saving, jedec soic, udfn, tssop, xdfn and vfbga packages. the at25010b/020b/040b is enabled through the chip select pin ( cs) and accessed via a three-wire interface consisting of serial data input (si), serial data output (so), and serial clock (sck). all programming cycles are completely self-timed, and no separate erase cycle is required before write. block write protection is enabled by programming the status register with one of four blocks of write protection. separate program enable and program disable instructions are provided for additional data protection. hardware data protection is provided via the wp pin to protect against inadvertent write attempts. the hold pin may be used to suspend any serial communication without resetting the serial sequence. table 0-1. pin configuration pin name function cs chip select sck serial data clock si serial data input so serial data output gnd ground v cc power supply wp write protect hold suspends serial input spi serial eeprom 1k (128x8) 2k (256x8) 4k (512x8) at25010b AT25020B at25040b preliminary v cc hold sck si cs so wp gnd 4 3 2 1 5 6 7 8 8-lead udfn, xdfn bottom view v cc hold sck si cs so wp gnd 1 2 3 4 8 7 6 5 8-ball vfbga bottom view 1 2 3 4 8 7 6 5 soic, tssop v cc hold sck si cs so wp gnd 8707b?seepr?3/10
2 8707b?seepr?3/10 at25010b/020b/040b [preliminary] 1. absolute maximum ratings* figure 1-1. block diagram operating temperature ? 40c to + 125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional opera- tion of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute max- imum rating conditions for extended peri- ods may affect device reliability. storage temperature ? 65c to + 150c voltage on any pin with respect to ground ? 1.0v to + 7.0v maximum operating voltage6.25v dc output current5.0 ma memory array 128/256/512 x 8 status register data register mode decode logic clock generator output buffer address decoder v cc
3 8707b?seepr?3/10 at25010b/020b/040b [preliminary] table 1-1. pin capacitance (1) note: 1. this parameter is characterized and is not 100% tested. table 1-2. dc characteristics (1) note: 1. v il min and v ih max are reference only and are not tested. applicable over recommended operating range from t a = 25c , f = 1.0 mhz, v cc = +5.0v (unless otherwise noted) symbol test conditions max units conditions c out output capacitance (so) 8 pf v out =0v c in input capacitance ( cs, sck, si, wp, hold) 6 pf v in =0v applicable over recommended operating range from: t ai = ? 40 ? cto+85 ? c, v cc = +1.8v to +5.5v, (unless otherwise noted) symbol parameter test condition min typ max units v cc1 supply voltage 1.8 5.5 v v cc2 supply voltage 2.5 5.5 v v cc3 supply voltage 4.5 5.5 v i cc1 supply current v cc = 5.0v at 20 mhz, so = open, read 8.5 10.0 ma i cc2 supply current v cc = 5.0v at 10 mhz, so = open, read, write 4.5 5.0 ma i cc3 supply current v cc = 5.0v at 1 mhz, so = open, read, write 2.0 3.0 ma i sb1 standby current v cc = 1.8v, cs = v cc 0.1 0.5 a i sb2 standby current v cc = 2.5v, cs = v cc 0.2 1.0 a i sb3 standby current v cc = 5.0v, cs = v cc 2.0 3.5 a i il input leakage v in =0vtov cc ? 3.0 a i ol output leakage v in =0vtov cc ,t ac = 0c to 70c ? 3.0 3.0 a v il (1) input low-voltage ? 0.6 v cc x 0.3 v v ih (1) input high-voltage v cc x 0.7 v cc + 0.5 v v ol1 output low-voltage 3.6v ? v cc ? 5.5v i ol = 3.0 ma 0.4 v v oh1 output high-voltage i oh = ? 1.6 ma v cc ? 0.8 v v ol2 output low-voltage 1.8v ? v cc ? 3.6v i ol = 0.15 ma 0.2 v v oh2 output high-voltage i oh = ? 100 a v cc ?? 0.2 v
4 8707b?seepr?3/10 at25010b/020b/040b [preliminary] table 1-3. ac characteristics applicable over recommended operating range from t ai = ? 40 to +85c, v cc = as specified, cl = 1 ttl gate and 30 pf (unless otherwise noted) symbol parameter voltage min max units f sck sck clock frequency 4.5 ? 5.5 2.5 ? 5.5 1.8 ?? 5.5 0 0 0 20 10 5 mhz t ri input rise time 4.5 ? 5.5 2.5 ? 5.5 1.8 ?? 5.5 2 2 2 s t fi input fall time 4.5 ? 5.5 2.5 ? 5.5 1.8 ?? 5.5 2 2 2 s t wh sck high time 4.5 ?? 5.5 2.5 ? 5.5 1.8 ?? 5.5 20 40 80 ns t wl sck low time 4.5 ? 5.5 2.5 ?? 5.5 1.8 ?? 5.5 20 40 80 ns t cs cs high time 4.5 ? 5.5 2.5 ? 5.5 1.8 ? 5.5 100 100 200 ns t css cs setup time 4.5 ? 5.5 2.5 ?? 5.5 1.8 ?? 5.5 100 100 200 ns t csh cs hold time 4.5 ? 5.5 2.5 ?? 5.5 1.8 ? 5.5 100 100 200 ns t su data in setup time 4.5 ?? 5.5 2.5 ?? 5.5 1.8 ??? 5.5 20 40 80 ns t h data in hold time 4.5 ? 5.5 2.5 - 5.5 1.8 - 5.5 20 40 80 ns t hd hold setup time 4.5 ? 5.5 2.5 ? 5.5 1.8 ?? 5.5 20 40 80 ns t cd hold hold time 4.5 ? 5.5 2.5 ? 5.5 1.8 ? 5.5 20 40 80 ns t v output valid 4.5 ?? 5.5 2.5 ?? 5.5 1.8 ? 5.5 0 0 0 20 40 80 ns t ho output hold time 4.5 ?? 5.5 2.5 ?? 5.5 1.8 ?? 5.5 0 0 0 ns t lz hold to output low z 4.5 ? 5.5 2.5 ? 5.5 1.8 ? 5.5 0 0 0 25 50 100 ns
5 8707b?seepr?3/10 at25010b/020b/040b [preliminary] note: 1. this parameter is characterized and is not 100% tested. 2. serial interface description master: the device that generates the serial clock. slave: because the serial clock pin (sck) is always an input, the at25010b/020b/040b always operates as a slave. transmitter/receiver: the at25010b/020b/040b has separate pins designated for data transmission (so) and reception (si). msb: the most significant bit (msb) is the first bit transmitted and received. serial op-code: after the device is selected with cs going low, the first byte will be received. this byte con- tains the op-code that defines the operations to be performed. the op-code also contains address bit a8 in both the read and write instructions. invalid op-code: if an invalid op-code is received, no data will be shifted into the at25010b/020b/040b, and the serial output pin (so) will remain in a high impedance state until the falling edge of cs is detected again. this will reinitialize the serial communication. chip select: the at25010b/020b/040b is selected when the cs pin is low. when the device is not selected, data will not be accepted via the si pin, and the so pin will remain in a high impedance state. hold: the hold pin is used in conjunction with the cs pin to select the at25010b/020b/040b. when the device is selected and a serial sequence is underway, h o l d can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, the hold pin must be brought low while the sck pin is low. to resume serial communication, the hold pin is brought high while the sck pin is low (sck may still toggle during hold). inputs to the si pin will be ignored while the so pin is in the high impedance state. write protect: the write protect pin ( w p) will allow normal read/write operations when held high. when the wp pin is brought low, all write operations are inhibited. wp going low while cs is still low will interrupt a write to the at25010b/020b/040b. if the internal write cycle has already been initiated, wp going low will have no effect on any write operation. t hz hold to output high z 4.5 ? 5.5 2.5 ? 5.5 1.8 ?? 5.5 25 50 100 ns t dis output disable time 4.5 ?? 5.5 2.5 ? 5.5 1.8 ?? 5.5 25 50 100 ns t wc write cycle time 4.5 ? 5.5 2.5 ? 5.5 1.8 ?? 5.5 5 5 5 ms endurance (1) 5.0v, 25 ? c, page mode 1m write cycles table 1-3. ac characteristics (continued) applicable over recommended operating range from t ai = ? 40 to +85c, v cc = as specified, cl = 1 ttl gate and 30 pf (unless otherwise noted) symbol parameter voltage min max units
6 8707b?seepr?3/10 at25010b/020b/040b [preliminary] figure 2-1. spi serial interface at25010b/020b/040b
7 8707b?seepr?3/10 at25010b/020b/040b [preliminary] 3. functional description the at25010b/020b/040b is designed to interface directly with the synchronous serial peripheral interface (spi) of the 6805 and 68hc11 series of microcontrollers. the at25010b/020b/040b utilizes an 8-bit instruction register. the list of instructions and their operation codes are contained in figure 3-1 . all instructions, addresses, and data are transferred with the msb first and start with a high-to-low cs transition. note: ?a? represents msb address bit a8. write enable (wren): the device will power up in the write disable state when v cc is applied. all program- ming instructions must therefore be preceded by a write enable instruction. the wp pin must be held high during a wren instruction. write disable (wrdi): to protect the device against inadvertent writes, the write disable instruction disables all programming modes. the wrdi instruction is independent of the status of the wp pin. read status register (rdsr): the read status register instruction provides access to the status register. the read/busy and write enable status of the device can be determined by the rdsr instruction. similarly, the block write protection bits indicate the extent of protection employed. these bits are set by using the wrsr instruction. table 3-1. instruction set for the at25010b/020b/040b instruction name instruction format operation wren 0000 x110 set write enable latch wrdi 0000 x100 reset write enable latch rdsr 0000 x101 read status register wrsr 0000 x001 write status register read 0000 a011 read data from memory array write 0000 a010 write data to memory array table 3-2. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xxxxbp1bp0wen rd y table 3-3. read status register bit definition bit definition bit0( rd y) bit 0 = ?0? ( rd y) indicates the device is ready. bit 0 = ?1? indicates the write cycle is in progress. bit 1 (wen) bit 1 = ?0? indicates the device is not write enabled. bit 1 = ?1? indicates the device is write enabled. bit 2 (bp0) see table 3-4 . bit 3 (bp1) see table 3-4 . bits 4?7 are ?0?s when device is not in an internal write cycle. bits 0?7 are ?1?s during an internal write cycle.
8 8707b?seepr?3/10 at25010b/020b/040b [preliminary] write status register (wrsr): the wrsr instruction allows the user to select one of four levels of protec- tion. the at25010b/020b/040b is divided into four array segments. one-quarter, one-half, or all of the memory segments can be protected. any of the data within any selected segment will therefore be read only. the block write protection levels and corresponding status register control bits are shown in table 3-4 . bits bp1 and bp0 are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., wren, t wc , rdsr). read sequence (read): reading the at25010b/020b/040b via the so pin requires the following sequence. after the c s line is pulled low to select a device, the read op-code (including a8) is transmitted via the si line fol- lowed by the byte address to be read (a7 ? a0). upon completion, any data on the si line will be ignored. the data (d7 ? d0) at the specified address is then shifted out onto the so line. if only one byte is to be read, the c s line should be driven high after the data comes out. the read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. when the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. write sequence (write): in order to program the at25010b/020b/040b, the write protect pin ( wp) must be held high and two separate instructions must be executed. first, the device must be write enabled via the wren instruction. then a write (write) instruction may be executed. also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. dur- ing an internal write cycle, all commands will be ignored except the rdsr instruction. a write instruction requires the following sequence. after the cs line is pulled low to select the device, the write op-code (including a8) is transmitted via the si line followed by the byte address (a7 ? a0) and the data (d7 ? d0) to be programmed. programming will start after the c s pin is brought high. the low-to-high transition of the c spin must occur during the sck low time immediately after clocking in the d0 (lsb) data bit. the ready/busy status of the device can be determined by initiating a read status register (rdsr) instruction. if bit 0 = ?1?, the write cycle is still in progress. if bi t 0 = ?0?, the write cycle has ended. only the rdsr instruction is enabled during the write programming cycle. the at25010b/020b/040b is capable of an 8-byte page write operation. after each byte of data is received, the three low-order address bits are internally incremented by one; the six high-order bits of the address will remain constant. if more than 8 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. the at25010b/020b/040b is automatically returned to the write disable state at the com- pletion of a write cycle. note: if the wp pin is brought low or if the device is not write enabled (wren), the device will ignore the write instruction and will return to the standby state, when cs is brought high. a new cs falling edge is required to reinitiate the serial communication. table 3-4. block write protect bits level status register bits array addresses protected bp1 bp0 at25010b AT25020B at25040b 0 0 0 none none none 1 (1/4) 0 1 60 ? 7f c0 ? ff 180 ?? ff 2 (1/2) 1 0 40 ? 7f 80 ? ff 100 ? 1ff 3 (all) 1 1 00 ? 7f 00 ? ff 000 ? 1ff
9 8707b?seepr?3/10 at25010b/020b/040b [preliminary] 4. timing diagrams figure 4-1. synchronous data timing (for mode 0) figure 4-2. wren timing figure 4-3. wrdi timing so hi-z hi-z t v valid in si t h t su t dis sck t wh t csh cs t css t cs t wl t ho v ih v il v ih v il v ih v il v oh v ol so si sck cs wren op-code hi-z so si sck cs wrdi op-code hi-z
10 8707b?seepr?3/10 at25010b/020b/040b [preliminary] figure 4-4. rdsr timing figure 4-5. wrsr timing figure 4-6. read timing so si sck cs 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 instruction 76543210 data out high impedance msb so si sck cs 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 instruction 76543210 data in high impedance so si sck cs 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 instruction byte address data out high impedance msb 76543210 76543210 9 th bit of address 8
11 8707b?seepr?3/10 at25010b/020b/040b [preliminary] figure 4-7. write timing figure 4-8. hold timing so si sck cs 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 instruction byte address data in high impedance 76543210 76543210 9 th bit of address 8 h old so sck cs t cd t cd t hd t hd t lz t hz
12 8707b?seepr?3/10 at25010b/020b/040b [preliminary] 5. ordering code detail atmel designator product family device density device revision shipping carrier option operating voltage 010 = 1k 020 = 2k 040 = 4k b or blank = bulk (tubes) t = tape and reel l = 1.8v to 5.5v package device grade or wafer/die thickness h = green, nipdau lead finish, industrial temperature range (-40?c to +85?c) u = green, matte sn lead finish, industrial temperature range (-40?c to +85?c) 11 = 11mil wafer thickness package option ss = jedec soic x = tssop ma = udfn me = xdfn c = vfbga wwu = wafer unsawn wdt = die in tape and reel at25010b-sshl-b
13 8707b?seepr?3/10 at25010b/020b/040b [preliminary] 6. part markings at25010b-sshl at25010b-xhl at25010b-cul line 1: atml=atmel h=material set/grade yww=date code line 2: 51b=at25010b, l=1.8 to 5.5v, @=country of origin line 3: atmel lot number |---|---|---|---|---|---|---|---| a t m l h y w w |---|---|---|---|---|---|---|---| 5 1 b l @ |---|---|---|---|---|---|---|---| atmel lot number |---|---|---|---|---|---|---|---| | pin 1 indicator (dot) line 1: at=atmel h=material set/grade yww=date code line 2: 51b=at25010b, l=1.8 to 5.5v, @=country of origin line 3: atmel lot number pin 1 indicator(dot) | |---|---|---|---|---|---| * a t h y w w |---|---|---|---|---|---| 5 1 b l @ |---|---|---|---|---|---|---| atmel lot number |---|---|---|---|---|---|---| line 1: 51b=at25010b, u=material set/grade line 2: ym=date code, xx=trace code |---|---|---|---| 5 1 b u |---|---|---|---| y m x x |---|---|---|---| |<-- pin 1 this corner
14 8707b?seepr?3/10 at25010b/020b/040b [preliminary] at25010b-mahl at25010b-mehl AT25020B-sshl line 1: 51b=at25010b line 2: h=material set/grade, l=1.8 to 5.5v, @=country of origin line 3: y=date code, xx=trace code |---|---|---| 5 1 b |---|---|---| h l @ |---|---|---| y x x |---|---|---| * | pin 1 indicator (dot) line 1: 51b=at25010b line 2: y=date code, xx=trace code |---|---|---| 5 1 b |---|---|---| y x x |---|---|---| * | pin 1 indicator (dot) line 1: atml=atmel h=material set/grade yww=date code line 2: 52b=AT25020B, l=1.8 to 5.5v, @=country of origin line 3: atmel lot number |---|---|---|---|---|---|---|---| a t m l h y w w |---|---|---|---|---|---|---|---| 5 2 b l @ |---|---|---|---|---|---|---|---| atmel lot number |---|---|---|---|---|---|---|---| | pin 1 indicator (dot)
15 8707b?seepr?3/10 at25010b/020b/040b [preliminary] AT25020B-xhl AT25020B-cul AT25020B-mahl line 1: at=atmel h=material set/grade yww=date code line 2: 52b=AT25020B, l=1.8 to 5.5v, @=country of origin line 3: atmel lot number pin 1 indicator (dot) | |---|---|---|---|---|---| * a t h y w w |---|---|---|---|---|---| 5 2 b l @ |---|---|---|---|---|---|---| atmel lot number |---|---|---|---|---|---|---| line 1: 52b=AT25020B, u=material set/grade line 2: ym=date code, xx=trace code |---|---|---|---| 5 2 b u |---|---|---|---| y m x x |---|---|---|---| |<-- pin 1 this corner line 1: 52b=AT25020B line 2: h=material set/grade, l=1.8 to 5.5v, @=country of origin line 3: y=date code, xx=trace code |---|---|---| 5 2 b |---|---|---| h l @ |---|---|---| y x x |---|---|---| * | pin 1 indicator (dot)
16 8707b?seepr?3/10 at25010b/020b/040b [preliminary] AT25020B-mehl at25040b-sshl at25040b-xhl line 1: 52b=AT25020B line 2: y=date code, xx=trace code |---|---|---| 5 2 b |---|---|---| y x x |---|---|---| * | pin 1 indicator (dot) line 1: at=atmel h=material set/grade yww=date code line 2: 54b=at25040b, l=1.8 to 5.5v, @=country of origin line 3: atmel lot number pin 1 indicator (dot) | |---|---|---|---|---|---| * a t h y w w |---|---|---|---|---|---| 5 4 b l @ |---|---|---|---|---|---|---| atmel lot number |---|---|---|---|---|---|---| line 1: at=atmel h=material set/grade yww=date code line 2: 54b=at25040b, l=1.8 to 5.5v, @=country of origin line 3: atmel lot number pin 1 indicator (dot) | |---|---|---|---|---|---| * a t h y w w |---|---|---|---|---|---| 5 4 b l @ |---|---|---|---|---|---|---| atmel lot number |---|---|---|---|---|---|---|
17 8707b?seepr?3/10 at25010b/020b/040b [preliminary] at25040b-cul at25040b-mahl at25040b-mehl line 1: 54b=at25040b, u=material set/grade line 2: ym=date code, xx=trace code |---|---|---|---| 5 4 b u |---|---|---|---| y m x x |---|---|---|---| |<-- pin 1 this corner line 1: 54b=at25040b line 2: h=material set/grade, l=1.8 to 5.5v, @=country of origin line 2: y=date code, xx=trace code |---|---|---| 5 4 b |---|---|---| h l @ |---|---|---| y x x |---|---|---| * pin 1 indicator (dot) line 1: 54b=at25040b line 2: y=date code, xx=trace code |---|---|---| 5 4 b |---|---|---| y x x |---|---|---| * | pin 1 indicator (dot)
18 8707b?seepr?3/10 at25010b/020b/040b [preliminary] 7. ordering codes at25010b ordering information (1) note: 1. bulk delivery in tubes (soic and tssop 100/tube). 2. tape and reel delivery (soic 4k/reel. tssop, udfn, xdfn and vfbga 5k/reel). 3. contact atmel sales for wafer sales. ordering code voltage package operation range at25010b-sshl-b (1) (nipdau lead finish) at25010b-sshl-t (2) (nipdau lead finish) at25010b-xhl-b (1) (nipdau lead finish) at25010b-xhl-t (2) (nipdau lead finish) at25010b-mahl-t (2) (nipdau lead finish) at25010b-mehl-t (2) (nipdau lead finish) at25010b-cul-t (2) (snagcu ball finish) 1.8v to 5.5v 1.8v to 5.5v 1.8v to 5.5v 1.8v to 5.5v 1.8v to 5.5v 1.8v to 5.5v 1.8v to 5.5v 8s1 8s1 8a2 8a2 8ma2 8me1 8u3-1 lead-free/halogen-free/ industrial temperature ( ? 40 to 85 ? c) at25010b-wwu11l (3) 1.8v to 5.5v die sale industrial temperature ( ? 40 to 85 ? c) package type 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) 8a2 8-lead, 0.170" wide, thin shrink small outline package (tssop) 8ma2 8-lead, 2.00mm x 3.00mm body, 0.50 mm pitch, dual no lead package (udfn) 8me1 8-lead (1.80x2.20mm body) extra thin dfn (xdfn) 8u3-1 8-ball die ball grid array (vfbga)
19 8707b?seepr?3/10 at25010b/020b/040b [preliminary] AT25020B ordering information (1) note: 1. bulk delivery in tubes (soic and tssop 100/tube). 2. tape and reel delivery (soic 4k/reel. tssop, udfn, xdfn and vfbga 5k/reel). 3. contact atmel sales for wafer sales. ordering code voltage package operation range AT25020B-sshl-b (1) (nipdau lead finish) AT25020B-sshl-t (2) (nipdau lead finish) AT25020B-xhl-b (1) (nipdau lead finish) AT25020B-xhl-t (2) (nipdau lead finish) AT25020B-mahl-t (2) (nipdau lead finish) AT25020B-mehl-t (2) (nipdau lead finish) AT25020B-cul-t (2) (snagcu ball finish) 1.8v to 5.5v 1.8v to 5.5v 1.8v to 5.5v 1.8v to 5.5v 1.8v to 5.5v 1.8v to 5.5v 1.8v to 5.5v 8s1 8s1 8a2 8a2 8ma2 8me1 8u3-1 lead-free/halogen-free/ industrial temperature ( ? 40 to 85 ? c) AT25020B-wwu11l (3) 1.8v to 5.5v die sale industrial temperature ( ? 40 to 85 ? c) package type 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) 8a2 8-lead, 0.170" wide, thin shrink small outline package (tssop) 8ma2 8-lead, 2.00mm x 3.00mm body, 0.50 mm pitch, dual no lead package (udfn) 8me1 8-lead (1.80x2.20mm body) extra thin dfn (xdfn) 8u3-1 8-ball die ball grid array (vfbga)
20 8707b?seepr?3/10 at25010b/020b/040b [preliminary] at25040b ordering information note: 1. bulk delivery in tubes (soic and tssop 100/tube). 2. tape and reel delivery (soic 4k/reel. tssop, udfn, xdfn and vfbga 5k/reel). 3. contact atmel sales for wafer sales. ordering code voltage package operation range at25040b-sshl-b (1) (nipdau lead finish) at25040b-sshl-t (2) (nipdau lead finish) at25040b-xhl-b (1) (nipdau lead finish) at25040b-xhl-t (2) (nipdau lead finish) at25040b-mahl-t (2) (nipdau lead finish) at25040b-mehl-t (2) (nipdau lead finish) at25040b-cul-t (2) (snagcu ball finish) 1.8v to 5.5v 1.8v to 5.5v 1.8v to 5.5v 1.8v to 5.5v 1.8v to 5.5v 1.8v to 5.5v 1.8v to 5.5v 8s1 8s1 8a2 8a2 8ma2 8me1 8u3-1 lead-free/halogen-free/ industrial temperature ( ? 40 to 85 ? c) at25040b-wwu11l (3) 1.8v to 5.5v die sale industrial temperature ( ? 40 to 85 ? c) package type 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) 8a2 8-lead, 0.170" wide, thin shrink small outline package (tssop) 8ma2 8-lead, 2.00mm x 3.00mm body, 0.50 mm pitch, dual no lead package (udfn) 8me1 8-lead, 1.80mm x 2.20mm body, extra thin dfn (xdfn) 8u3-1 8-ball die ball grid array (vfbga)
21 8707b?seepr?3/10 at25010b/020b/040b [preliminary] 8. packaging information 8s1 ? jedec soic package drawing contact: packagedrawings@atmel.com drawing no. rev. title gpc 8s1 e 12/11/09 8s1, 8-lead, (0.150? wide body), plastic gull wing outline (jedec soic) swb ? ? ? ? ? ? ? 1.27 bsc ? ? 1.75 0.25 0.51 0.25 5.05 3.99 6.20 1.27 8? common dimensions (unit of measure = mm) symbol min nom max note 1.35 0.10 0.31 0.17 4.80 3.81 5.79 0.40 0? a a1 b c d e1 e e l notes: 1. these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. e 1 2 3 4 8 7 6 5 gnd nc nc nc sda scl nc v cc ? c e1 l a b a1 e d end view top view side view
22 8707b?seepr?3/10 at25010b/020b/040b [preliminary] 8a2 ? tssop common dimensions (unit of measure = mm) symbol min nom max note package drawing contact: packagedrawings@atmel.com drawing no. rev. title gpc 8a2 d 12/11/09 notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 8a2, 8-lead, 4.4mm body, plastic thin shrink small outline package (tssop) tnr 2.90 4.30 ? 0.80 0.19 0.45 d e e1 a a2 b e l l1 3.00 6.40 bsc 4.40 ? 1.00 ? 0.65 bsc 0.60 1.00 re3 13.10 4.50 1.20 1.05 0.30 0.75 2, 5 3, 5 4 end view top view l l1 1 2 3 4 e1 pin 1 indicator this corner e gnd nc nc nc 8 7 6 5 sda scl nc v cc side view a2 a d b e
23 8707b?seepr?3/10 at25010b/020b/040b [preliminary] 8ma2 ? udfn common dimensions (unit of measure = mm) symbol min nom max note package drawing contact: packagedrawings@atmel.com drawing no. rev. title gpc 8ma2 a 4/15/08 notes: 1. this drawing is for general information only. refer to jedec drawing mo-229 for proper dimensions, tolerances, datums, etc. 2. the terminal #1 id is a laser-marked feature. 3. dimensions b applies to metalized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 8ma2 , 8-pad, 2 x 3 x 0.6 mm body, thermally enhanced plastic ultra thin dual flat no lead package (udfn) ynz 1.40 1.20 0.50 0.00 ? 0.30 0.18 0.20 d e d2 e2 a a1 a2 c l e b k 2.00 bsc 3.00 bsc 1.50 1.30 0.55 0.02 ? 0.152 ref 0.35 0.50 bsc 0.25 ? 1.60 1.40 0.60 0.05 0.55 0.40 0.30 ? 3 c e a a1 a2 pin 1 id d 8 7 6 5 1 2 3 4 d2 e2 e (6x) l (8x) b (8x) pin#1 id (r0.10) 0.35 k 1 2 3 4 8 7 6 5
24 8707b?seepr?3/10 at25010b/020b/040b [preliminary] 8me1 ? xdfn common dimensions (unit of measure = mm) symbol min nom max note package drawing contact: packagedrawings@atmel.com drawing no. rev. title gpc 8me1 a 8/3/09 8me1, 8-lead (1.80 x 2.20 mm body) extra thin dfn (xdfn) dtp ? 0.00 1.70 2.10 0.15 0.26 a a1 d e b e e1 l ? ? 1.80 2.20 0.20 0.40 typ 1.20 ref 0.30 0.40 0.05 1.90 2.30 0.25 0.35 bottom view top view side view 8 7 6 5 1 2 3 4 d e pin #1 id a1 a pin #1 id e1 b l e b 0.10 0.15
25 8707b?seepr?3/10 at25010b/020b/040b [preliminary] 8u3-1 ? vfbga common dimensions (unit of measure = mm) symbol min nom max note package drawing contact: packagedrawings@atmel.com drawing no. rev. title po8u3-1 c 9/19/07 8u3-1, 8-ball, 1.50 x 2.00 mm body, 0.50 mm pitch, vfbga package (dbga2) 0.73 0.09 0.40 0.20 a a1 a2 b d e e e1 d d1 0.79 0.14 0.45 0.25 1.50 bsc 2.00 bsc 0.50 bsc 0.25 ref 1.00 bsc 0.25 ref 0.85 0.19 0.50 0.30 2 top view end view notes: 1. this drawing is for general information only. 2. dimension ?b? is measured at maximum solder ball diameter. 3. solder ball composition shall be 95.5sn-4.0ag-.5cu e d pin 1 ball pad corner b 1. a 1 a a 2 8 7 6 5 1 2 3 4 bottom view (8 solder balls) pin 1 ball pad corner (d1) d (e1) e
26 8707b?seepr?3/10 at25010b/020b/040b [preliminary] 9. revision history doc. rev. date comments 8707b 3/2010 replace 8y6 with 8ma2 8707a 2/2010 initial document release
8707b?seepr?3/10 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (852) 2245-6100 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support s_eeprom@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or inciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to s pecifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained herein. unless specifica lly provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. ? 2010 atmel corporation . all rights reserved. atmel ? , logo and combinations thereof, everywhere you are ? and others, are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

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